1. Field of the Invention
The present invention relates to an image pickup device.
Priority is claimed on Japanese Patent Application No. 2012-129765, filed Jun. 7, 2012, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
Japanese Unexamined Patent Application, First Publication No. 2005-347931 and Japanese Unexamined Patent Application, First Publication No. 2009-33297 disclose known examples of the configurations of image pickup devices in accordance with the related art. First, the configuration and process of an image pickup device in accordance with Japanese Unexamined Patent Application, First Publication No. 2005-347931 will be described.
FIG. 18 is a diagram illustrating the configuration of a (C)MOS sensor in accordance with the first related art disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-347931. An image pickup device 1001 illustrated in FIG. 18 includes an image capturing unit 1002, a vertical selection unit 1012, a reading current source unit 1005, an analog unit 1006, a count unit 1018, a ramp unit 1019, a column processing unit 1015, a horizontal selection unit 1014, an output unit 1017, and a control unit 1020.
The control unit 1020 controls each unit such as the vertical selection unit 1012, the reading current source unit 1005, the analog unit 1006, the count unit 1018, the ramp unit 1019, the column processing unit 1015, the horizontal selection unit 1014, and the output unit 1017. The image capturing unit 1002 includes unit pixels 1003 that each include a photoelectric conversion element and are arrayed in a matrix form. The image capturing unit 1002 generates a pixel signal according to the amount of an incident electromagnetic wave and outputs the pixel signal to a vertical signal line 1013 installed for each column.
The vertical selection unit 1012 controls a row address and row scanning of the image capturing unit 1002 via a row control line 1011, when each unit pixel 1003 of the image capturing unit 1002 is driven. The horizontal selection unit 1014 controls a column address and column scanning of a column AD conversion unit 1016 of the column processing unit 1015. The reading current source unit 1005 is a current source that reads a pixel signal from the image capturing unit 1002 as a voltage signal. The analog unit 1006 performs amplification or the like, as necessary.
The column processing unit 1015 includes the column AD conversion unit 1016 (column unit) that includes a comparison unit 1109 and a latch unit 1108 for each column of the unit pixels 1003. A digital value output from the count unit 1018 is input to the ramp unit 1019. The ramp unit 1019 generates a ramp wave according to the input digital value and outputs the ramp wave as a reference signal to one of the input terminals of the comparison unit 1109. The output of the count unit 1018 is distributed to the latch unit 1108 of the respective columns. The pixel signal is input as an analog signal to be subjected to AD conversion from the unit pixel 1003 to the other of the input terminals of the comparison unit 1109 at each column in the column AD conversion unit 1016 via the vertical signal line 1013.
The horizontal selection unit 1014 controls a column address and column scanning of each AD conversion unit 1016 in the column processing unit 1015. Accordingly, digital data subjected to the AD conversion is sequentially output to the output unit 1017 via a horizontal signal line.
Next, a process in accordance with the first related art, and particularly, an AD conversion process will be described. First, the count unit 1018 starts counting in synchronization with a clock signal input from the control unit 1020. Simultaneously, the ramp unit 1019 starts generating the ramp wave. A common ramp wave of each column varying in synchronization with a pixel signal read from the unit pixel 1003 of each column and a count value of the count unit 1018 is input to the comparison unit 1109 of each column. In parallel with the ramp wave, the count value of the count unit 1018 is distributed to the latch unit 1108. When a magnitude relation between two input signals to the comparison unit 1109 of a given column is changed, the comparison output of the comparison unit 1109 is inverted and the latch unit 1108 of that row retains the count value. Through the above-described process, the pixel signal read from the pixel is subjected to the AD conversion, and thus a value (digital value) retained in the latch unit 1108 is obtained.
Here, the description of a specific process of the unit pixel will be omitted, but a reset level and a signal level are output from the unit pixel, as known in the related art. In order to acquire the digital value of a signal component (a difference signal between the reset level and the signal level) with high accuracy, the reset level and the signal level are required to be subjected to subtraction (CDS process) in a digital region. In the configuration of the first related art, in order to acquire the digital value of a signal component, the subtraction (CDS process) is performed using an arithmetic unit provided outside the column unit after the digital values of the reset level and the signal level are retained in the latch unit 1108 in the column unit.
Next, an image pickup device in accordance with Japanese Unexamined Patent Application, First Publication No. 2009-33297 will be described. The image pickup device in accordance with the second related art disclosed in Japanese Unexamined Patent Application, First Publication No. 2009-33297 is configured to further improve a resolution by setting a count value of the count unit 1018 as data of high-order bits and delays the phase of a clock (count clock) input to the count unit 1018 to generate a multi-phase clock and setting the logic state as data of low-order bits.
Here, an imager used in a digital still camera (DSC) will be considered as an example of a specific device. Specifically, a specification in which the number of pixels is 20 million and a frame rate is 60 frame/sec will be assumed. When it is assumed to facilitate the description that the pixel array of the 20 million pixels is 4000 rows×5000 columns and there is no blanking period for further simplification, a reading period of one row is as follows:60 frame/sec×4000 row/frame=240 Kline/sec.That is a reading rate of one row is 240 KHz. When this device is realized as the image pickup device in accordance with the first related art, in a case of AD conversion of 12 bits, 212=4096 gray scales are required to be compared for the reading time of one row. Therefore, a count value of the count unit 1018 output to a digital memory is required to be changed at about 960 MHz which is about 4 thousand times the reading rate of one row.
In this calculation, a period, such as a standby time until an AD conversion circuit receives data from a pixel, in which a comparison process may not be performed as the AD conversion is not considered. Further, an OB (Optical Black) pixel period or the like is excluded in addition to the above period. Therefore, in practice, the frequency may be greater than the frequency estimated in the above-described way.
Next, when the above-described device is realized as the image pickup device in accordance with the second related art, the same calculation will be made. For example, on the assumption that 12 bits constitute 8 high-order bits and 4 low-order bits, it is sufficient for the count value of the count unit 1018 output to the digital memory to be changed at about 60 MHz which is 256 times the reading rate of one row. In regard to the low-order bits, digital values are acquired by delaying the phase of the clock (count clock) input to the count unit 1018 by 0, π/16, π/8, 3π/16, π/4, 5π/16, 3π/8, 7π/16, π/2, 9π/16, 5π/8, 11 π/16, 3π/4, 13π/16, 7π/8, and 15π/16, and retaining and encoding the logic states. Even in the configuration of the second related art, as in the first related art, the subtraction (CDS process) is required to be performed using an arithmetic unit provided outside the column unit, and thus encoding of the data of the low-order bits is required in addition to the subtraction (CDS process).